1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a fabricating method thereof that are capable of reducing the number of masks and the process time of fabrication.
2. Discussion of the Related Art
A liquid crystal display (LCD) of an active matrix driving system may use thin film transistors (TFTs) as switching devices to display a natural moving picture. Since LCDs can be formed into smaller devices than existing Brown tubes, they are used commonly in computer monitors and laptops, in office automation equipment such as copy machines, and in portable equipment such as cellular phones and pagers.
An active matrix LCD displays a picture corresponding to video signals, such as television signals, typically on a pixel (or picture element) matrix having pixels arranged at each intersection of gate lines and data lines. Each pixel includes a liquid crystal cell that controls a transmitted light quantity according to a voltage level of a data signal from a data line. A TFT is installed at an intersection of the gate line and the data line to switch a data signal to the liquid crystal cell in response to a scanning signal (i.e., a gate pulse) from the gate line.
The operation of LCDs can be classified primarily into two modes: a twisted nematic (TN) mode, in which a vertical electric field is applied, and an in-plane switching (IPS) mode, in which a horizontal electric field is applied to have a wide viewing angle, depending on the direction of an electric field driving the liquid crystal.
FIG. 1 shows an electrode arrangement at a TFT substrate of a conventional TN mode LCD device, and FIG. 2 is a section view of the TFT substrate taken along the A-A′ line in FIG. 1.
As shown in FIG. 1 and FIG. 2, the LCD device includes a TFT provided at an intersection of a gate line 15 and a data line 13, and a pixel electrode 26 provided in a pixel area near the intersection of the gate line 15 and the data line 13.
The TFT is formed by sequentially depositing a gate electrode 12, a gate insulating film 14, an active layer 16, an ohmic contact layer 18, a source electrode 20 and a drain electrode 22, a protective layer 24, a pixel electrode 26 and an alignment film 28 on a substrate 10. The gate electrode 12 is connected to the gate line 15 and the source electrode 20 is connected to the data line 13.
The TFT applies a data signal from the data line 13 to the pixel electrode 26, and applies a scanning pulse to the gate electrode 12 to drive a liquid crystal cell. The pixel electrode 26 is formed on a portion of the protective layer 24 and on a portion of the drain electrode 22 exposed by a contact hole 30 formed in the protective layer 24. The pixel electrode 26 is formed of a transparent conductive material such as such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO). The gate insulating film 14 is formed of an inorganic insulating material, and the protective layer 24 is formed of an organic insulating material.
FIGS. 3A to 3G show steps of a method of fabricating the TFT shown in FIG. 2.
As shown in FIG. 3A, the gate electrode 12 is formed on the transparent substrate 10 by using a sputtering technique to deposit a metal thin film layer on the transparent substrate 10 and patterning it by photolithography and wet etching. The gate electrode 12 is formed of a metal material such as aluminum (Al), copper (Cu) or chrome (Cr), and a (NH4)2S2O8 aqueous solution is used as an etchant for wet etching.
As shown in FIG. 3B, the gate insulating film 14, the active layer 16 and the ohmic contact layer 18 are formed sequentially on the transparent substrate 10 and the gate electrode 12. The gate insulating film 14 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) onto the transparent substrate 10 by a chemical vapor deposition (CVD) technique. An amorphous silicon (a-Si) layer and an amorphous silicon layer doped with an impurity (n+ a-Si) are sequentially deposited onto the gate insulating film 14. The active layer 16 and the ohmic contact layer 18 are formed by patterning the layers of a-Si and n+ a-Si by photolithography and dry etching.
As shown in FIG. 3C, the source electrode 20 and the drain electrode 22 are formed on the ohmic contact layer 18. The source electrode 20, the drain electrode 22, and the data line 13 are formed by depositing a metal layer on the gate insulating film 14 in such a manner as to cover the ohmic contact layer 18 using a sputtering technique and then patterning it using photolithography and wet etching. The source electrode 20 and the drain electrode 22 are formed of molybdenum (Mo) or a molybdenum alloy such as MoW, MoTa or MoNb, and use a (NH4)2S2O8 aqueous solution as an etchant.
Subsequently, as shown in FIG. 3D, the exposed ohmic contact layer 18 is dry etched by using the source electrode 20 and the drain electrode 22 as a mask to thereby expose the active layer 16 through the ohmic contact layer 18, source electrode 20 and the drain electrode 22.
As shown in FIG. 3E, the protective layer 24 is formed on portions of the gate insulating film 14, the source electrode 20 and the drain electrode 22. The protective layer 24 is formed by depositing an insulating material and then patterning it. The contact hole 30 is formed in the protective layer 24 and exposes a portion of the drain electrode 22. The protective layer 24 is formed of an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material having a small dielectric constant, such as an acrylic organic compound, Teflon, BCB (benzocyclobutene), Cytop or PFCB (perfluorocyclobutane).
As shown in FIG. 3F, the pixel electrode 26 is formed on the protective layer 24 and on the portion of the drain electrode 22 exposed by the contact hole 30. The pixel electrode 26 is formed by depositing a transparent conductive material on the protective layer 24 and then patterning the material. The pixel electrode 26 is formed of ITO, IZO or ITZO. The pixel electrode 26 electrically contacts the drain electrode 22 through the contact hole 30.
As shown in FIG. 3G, the alignment film 28 is formed on the protective layer 24 and the pixel electrode 26. Prior to the formation of the alignment film 28, an annealing is carried out on all of the layers. Furthermore, the TFT is tested by applying an electrical signal to confirm that the TFT is functioning normally in its on and off states of operation.
If the test indicates that the TFT is functionally normally, then a primary alignment film of less than 1000 Å is formed by printing polyimide using a roller and thereafter the normal alignment film 28 is formed by rubbing the surface of the primary alignment film.
FIG. 4 shows an electrode arrangement at a TFT substrate of a conventional IPS mode LCD device, and FIG. 5 is a section view of the TFT substrate taken along the B-B′ line in FIG. 4.
As shown in FIG. 4 and FIG. 5, the IPS mode LCD device includes a TFT provided at an intersection of a gate line 35 and a data line 33, and a pixel electrode 46 and a common electrode 44 provided at a pixel area near the intersection of the gate line 35 and the data line
The TFT is formed on a transparent substrate 31 and includes a gate electrode 32 connected to the gate line 35, a source electrode 40 connected to the data line 33 and a drain electrode 42 connected to the pixel electrode 46.
The gate electrode 32, the gate line 35 and the common electrode 44 are formed by depositing a metal such as aluminum (Al), copper (Cu) or chrome (Cr), etc. onto the transparent substrate 31 and then patterning it. Herein, the common electrode 44 is patterned in a three-line stripe shape within the pixel cell area.
A gate insulating film 34 made from an inorganic dielectric material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the surfaces of the substrate 31, the gate electrode 32 and the common electrode 44. An active layer 36 formed of a-Si is deposited on the gate insulating film 34 and an ohmic contact layer 38 formed of a-Si doped with n+ ions is deposited on the active layer 36. The source electrode 40, the drain electrode 42 and the data line 33 formed of a metal are deposited on the ohmic contact layer 38. The source electrode 40 and the drain electrode 42 are patterned in such a manner to be spaced from each other by a predetermined channel width. The pixel electrode 46 is formed by depositing ITO onto a portion of the drain electrode 42 and the gate insulating film 34 and then patterning the deposited material. The pixel electrode 46 is patterned in a two-line stripe shape within the pixel cell area that alternates with the common electrode 44. Subsequently, the ohmic contact layer 38 provided in the space defined by the predetermined channel width between the source electrode 40 and the drain electrode 42 is etched to expose the active layer 36. A protective layer 48, formed of an inorganic insulating material or an organic insulating material having a small dielectric constant, is deposited on the exposed surfaces of the gate insulating film 34, the active layer 36, the source electrode 40, the drain electrode 42, and the pixel electrode 46.
Finally, an the alignment film 50 is formed on the protective film 48. Prior to the formation of the alignment film 50, an annealing is carried out on all of the layers. Furthermore, the TFT is tested by applying an electrical signal to confirm that the TFT is functioning normally in its on and off states of operation.
If the test indicates that the TFT is functioning normally, then a primary alignment film of less than 1000 Å is formed by printing polyimide using a roller and thereafter the normal alignment film 50 is formed by rubbing the surface of the primary alignment film.
However, in fabricating the conventional TN or IPS mode LCD device, the number of mask processes, such as the formation of the protective film, becomes excessive. Thus, the long process time required for the fabrication is a disadvantage of the conventional TN or IPS mode LCD device.